Appendix F: The 65C816 Processor

Overview
Compatibility with the 65C02
Registers
Status Flags
16 bit mode
Address Modes
Vectors
Instruction Tables

Overview

This document is a brief introduction and quick reference for the 65C816 Microprocessor. For more details, see the 65C816 data sheet or Programming the 65816: Including the 6502, 65C02, and 65802.

The WDC65C816 CPU is an 8/16 bit CPU and a follow-up to the 65C02 processor. The familiar 65C02 instructions and address modes are retained, and some new ones are added.

The CPU can optionally operate in 16-bit mode, extending the utility of math instruction (16-bit adds!) and the coverage of .X and .Y indexed modes to 64KB.

Zero Page has been renamed to Direct Page, and Direct Page can now be relocated anywhere in the first 64K of RAM. As a result, all of the Zero Page instructions are now “Direct” instructions and can operate anywhere in the X16’s address range.

Likewise, the Stack can also be relocated, and the stack pointer is now 16 bits. This allows for a much larger stack, and the combination of stack and DP relocation offer interesting multitasking opportunities.

Compatibility with the 65C02

The 65C916 CPU is generally compatible with the 65C02 instruction set, with the exception of the BBRx, BBSx, RMBx, and SMBx instructions. We recommend programmers avoid these instructions when writing X16 softwware, using the more conventional Boolean logic instructions, instead.

Registers

Notation	Name	Description
A	Accumulator	The accumulator. It stores the result of moth math and logical operations.
X	X Index	.X is mostly used as a counter and to offset addresses with X indexed modes
Y	Y Index	.Y is mostly used as a counter and to offset addresses with Y indexed modes
S	Stack Pointer	SP points to the next open position on the stack.
DB or DBR	Data Bank	Data bank is the default bank for operations that use a 16 bit address.
K or PBR	Program Bank	The default address for 16 bit JMP and JSR oprerations. Can only be set with a 24 bit JMP or JSR.
P	Processor Status	The flags.
PC	Program Counter	The address of the current CPU instruction

.A, .X, and .Y can be 8 or 16 bits wide, based on the flag settings (see below).

The Stack Pointer (.S) is 16 bits wide in Native mode and 8 bits wide (and fixed to the $100-1FF range) in Emulation mode.

.DB and .K are the bank registers, allowing programs and data to occupy separate 64K banks on computers with more than 64K of RAM. (The X16 does not use the bank registers, instead using addresses $00 and $01 for banking.)

Status Flags

The native mode flags are as follows:

nvmx dizc e

n = Negative
v = oVerflow
m = Memory width (0=16 bit, 1=8 bit)
x = Index register width (0=16 bit, 1=8 bit)
d = Decimal Mode
i = Interupts Disabled
z = Zero
c = Carry
e = Emulation Mode (0=65C02 mode, 1=65C816 mode)

In emulation mode, the m and x flags are always set to 1.

Here are the 6502 and 65C02 registers, for comparison:

nv1b dizc

n = Negative
v = oVerflow
1 = this bit is always 1
b = brk: set during a BRK instruction interrupt
d = Decimal Mode
i = Interupts Disabled
z = Zero
c = Carry

Note the missing b flag on the 65C816. This is no longer needed in native mode, since the BRK instruction now has its own vector.

The e flag can only accessed via the XCE instruction, which swaps Carry and the Emulation flag.

The other flags can all be manipulated with SEP and REP, and the various branch instructions (BEQ, BCS, etc) test some of the flags. The rest can only be tested indirectly through the stack.

When a BRK or IRQ is triggered in emulation mode, a ghost b flag will be pushed to the stack instead of the x flag. This can be used to test for a BRK vs IRQ in the Interrupt handler.

16 bit mode

The 65C816 CPU boots up in emulation mode. This locks the register width to 8 bits and locks out certain operations.

If you want to use the ‘816 features, including 16-bit operation, you will need to enable native mode. Clearing e switches the CPU to native mode. However, it’s not as simple as just setting a flag. The e flag can only be accessed through the XCE instruction, which swaps the Carry and Emulation flags.

To switch to native mode, use the following steps:

CLC  ; clear the Carry bit
XCE  ; swap the Emulation and Carry bit

To switch back to emulation mode, set the Carry flag and perform an XCE again.

SEC  ; Set Carry
XCE  ; and push the 1 into the Emulation flag.

Once e is cleared, the m and x flags can be set to 1 or 0 to control the register width.

When the m flag is clear, Accumulator operations and memory reads and writes will be 16-bit operations. The CPU reads two bytes at a time with LDA, writes two bytes at a time with STA, and all math involving .A is 16 bits wide.

Likewise, whenn x is clear, the .X and .Y index registers are 16 bits wide. INX and INY will now count up to 65535, and indexed instructions like LDA addr,X can now cover 64K.

You can use REP #$10 to enable 16-bit index registers, and REP #$20 to enable 16-bit memory and Accumulator. SEP #$10 or SEP #$20 will switch back to 8-bit operation. You can also combine the operand and use SEP #$30 or REP #$30 to flip both bits at once.

And now we reach the 16-bit assembly trap: the actual assembly opcodes are the same, regardless of the x and m flags. This means the assembler needs to track the state of these flags internally, so it can correctly write one or two bytes when assembling immediate mode instructions like LDA #$01.

You can help the assembler out by using hints. Different assemblers have different hinting systems, so we will focus on 64TASS and cc65.

64TASS accepts .as (.A short) and .al (.A long) to tell the assembler to store 8 bits or 16 bits in an immediate mode operand. For LDX and LDY, use the .xs and .xl hints.

The hints for ca65 are .a8, .a16, .i8, and .i16

Note that this has no effect on absolute or indirect addressing modes, such as LDA $1234 and LDA ($1000), since the operand for these modes is always 16 bits.

To make it easy to remember the modes, just remember that e, m, and x all emulate 65C02 behavior when set.

Address Modes

The 65C816 now has 24 discinct address modes, although most are veriations on a theme. Make note of the new syntax for Stack relative instructions (,S), the use of brackets for [24 bit indirect] addressing, and the fact that Zero Page has been renamed to Direct Page. This means that $0001 and $01 are now two different addresses (although they would be the same if .DP is set to $00.

Mode	Syntax	Description
Immediate	#$12	Value is supplied in the program stream
Absolute	$1234	Data is at this address.
Absolute X Indexed	$1234,X	Address is offset by X. If X=2 this is $1236.
Absolute Y Indexed	$1234,Y	Address is offset by X. If Y=2 this is $1236.
Direct	$12	Direct Page address. Operand is 1 byte.
Direct X Indexed	$12,X	Address on Direct Page is offset by .X
Direct Y Indexed	$12,Y	Address on Direct Page is offset by .Y
Direct Indirect	($12)	Value at $12 is a 16-bit address.
Direct Indirect Y Indexed	($12),Y	Resolve pointer at $12 then offset by Y.
Direct X Indexed Indirect	($12,X)	Start at $12, offset by X, then read that address.
Direct Indirect Long	[$12]	24 bit pointer on Direct Page.
Direct Indrect Long Y Indexed	[$12],Y	Resolve address at $12, then offset by Y.
Indirect	($1234)	Read pointer at $1234 and get data from the resultant address
Indirect X Indexed	($1234,X)	Read pointer at $1234 offset by X, get data from resultant address
Indirect Long	[$1234]	Pointer is a 24-bit address.
Absolute Long	$123456	24 bit address.
Absolute Indexed Long	$123456,X	24 bit address, offset by X.
Stack Relative Indexed	$12,S	Stack relative.
Stack Relative Indirect Indexed	($12,S),Y	Resolve Pointer at $12, then offset by Y.
Accumulator (implied)		Operation acts on .A
Implied		Target is part of the opcode name.
Relative Address (8 bit signed)	$1234	Branches can only jump by -128 to 127 bytes.
16 bit relative address	$1234	BRL can jump by 32K bytes.
Block Move	#$12,#$34	Operands are the bank numbers for block move/copy.

Vectors

The 65816 has two different sets of interrupt vectors. In emulation mode, the vectors are the same as the 65C02. In native mode (.e = 0), the native vectors are used. This allows you to switch to the desired operation mode, based on the operating mode of your interrupt handlers.

The Commander X16 operates mostly in emulation mode, so native mode interrupts on the X16 will switch to emulation mode, then simply call the 8-bit interrupt handlers.

The vectors are:

Name	Emu	Native
COP	FFF4	00FFE4
BRK	FFFE	00FFE6
ABORT	FFF8	00FFE8
NMI	FFFA	00FFEA
RESET	FFFC
IRQ	FFFE	00FFEE

The 65C02 shares the same interrupt for BRK and IRQ, and the b flag tells the interrupt handler whether to execute a break or interrupt.

In emulation mode, the 65C816 pushes a modified version of the flags to the stack. The BRK instruction actually pushes a 1 in bit 4, which can then be tested in the Interrupt Service Routine. In native mode, however, the flags are pushed verbatim, since BRK has its own handler.

There is also no native RESET vector, since the CPU always boots to emulation mode. The CPU always starts at the address stored in $FFFC.

Decimal Mode

When the d flag is set, the CPU operates in Decimal mode. In this mode, a byte is treated as two decimal digits, rather than a binary number. As a result, you can easily add, subtract, and display decimal numbers.

While in Decimal mode, the lower nibble of a byte contains the 1s digit, and the upper nibble contains the 10s digit. Each nibble can only contain value from 0-9, and addition will wrap from 9 to 0. Subtraction works similarly, wrapping down from 0 to 9.

SED enables Decimal mode. At that point, ADC and SBC will perform base-10 addition and subtraction. CLD clears Decimal mode and returns to binary mode.

When adding, the Carry bit will be set if the result is 100 or greater. The total result can never exceed 199, so two digits plus Carry is all that is needed to represent values from 0 to 199.

If you perform an ADC with the Carry bit set, this will add an extra 1 to the result.

Examples

Operation	.A	Result	Notes
ADC #$01	$09	$10
ADC #$01	$99	$00	Carry is set, indicating 100.

When subtracting, the Carry bit operates as a borrow bit, and the sense is inverted: 0 indicates a borrow took place, and 1 means it did not.

Operation	.A	Result	Notes
SBC #$01	$10	$09	Carry is set, indicating no borrow.
SBC #$01	$00	$99	Carry is clear, indicating a borrow.

In the second example ($00 - $01), the final result was $99 with a borrow.

Note that the n flag tracks the high bit, but two’s complement doesn’t work as expected in Decimal mode. Instead, we have to use Ten’s complement.

Simply put, $00 - $01 gives you $99. So when working in signed BCD, any value where the high digit is 5-9 is actually a negative value. To convert negative values to positive values for printing, you would subtract from 99 and add 1.

For example: the integer -49 is $51 in BCD. 99 - 51 + 1 = 49. You’d print that as -49.

Instruction Tables

Instructions By Opcode

	x0	x1	x2	x3	x4	x5	x6	x7	x8	x9	xA	xB	xC	xD	xE	xF
0x	BRK	ORA	COP	ORA	TSB	ORA	ASL	ORA	PHP	ORA	ASL	PHD	TSB	ORA	ASL	ORA
1x	BPL	ORA	ORA	ORA	TRB	ORA	ASL	ORA	CLC	ORA	INC	TCS	TRB	ORA	ASL	ORA
2x	JSR	AND	JSL	AND	BIT	AND	ROL	AND	PLP	AND	ROL	PLD	BIT	AND	ROL	AND
3x	BMI	AND	AND	AND	BIT	AND	ROL	AND	SEC	AND	DEC	TSC	BIT	AND	ROL	AND
4x	RTI	EOR	WDM	EOR	MVP	EOR	LSR	EOR	PHA	EOR	LSR	PHK	JMP	EOR	LSR	EOR
5x	BVC	EOR	EOR	EOR	MVN	EOR	LSR	EOR	CLI	EOR	PHY	TCD	JML	EOR	LSR	EOR
6x	RTS	ADC	PER	ADC	STZ	ADC	ROR	ADC	PLA	ADC	ROR	RTL	JMP	ADC	ROR	ADC
7x	BVS	ADC	ADC	ADC	STZ	ADC	ROR	ADC	SEI	ADC	PLY	TDC	JMP	ADC	ROR	ADC
8x	BRA	STA	BRL	STA	STY	STA	STX	STA	DEY	BIT	TXA	PHB	STY	STA	STX	STA
9x	BCC	STA	STA	STA	STY	STA	STX	STA	TYA	STA	TXS	TXY	STZ	STA	STZ	STA
Ax	LDY	LDA	LDX	LDA	LDY	LDA	LDX	LDA	TAY	LDA	TAX	PLB	LDY	LDA	LDX	LDA
Bx	BCS	LDA	LDA	LDA	LDY	LDA	LDX	LDA	CLV	LDA	TSX	TYX	LDY	LDA	LDX	LDA
Cx	CPY	CMP	REP	CMP	CPY	CMP	DEC	CMP	INY	CMP	DEX	WAI	CPY	CMP	DEC	CMP
Dx	BNE	CMP	CMP	CMP	PEI	CMP	DEC	CMP	CLD	CMP	PHX	STP	JML	CMP	DEC	CMP
Ex	CPX	SBC	SEP	SBC	CPX	SBC	INC	SBC	INX	SBC	NOP	XBA	CPX	SBC	INC	SBC
Fx	BEQ	SBC	SBC	SBC	PEA	SBC	INC	SBC	SED	SBC	PLX	XCE	JSR	SBC	INC	SBC

Instructions By Name


ADC	AND	ASL	BCC	BCS	BEQ	BIT	BMI	BNE	BPL
BRA	BRK	BRL	BVC	BVS	CLC	CLD	CLI	CLV	CMP
COP	CPX	CPY	DEC	DEX	DEY	EOR	INC	INX	INY
JMP	JML	JSL	JSR	LDA	LDX	LDY	LSR	MVN	MVP
NOP	ORA	PEA	PEI	PER	PHA	PHB	PHD	PHK	PHP
PHX	PHY	PLA	PLB	PLD	PLP	PLX	PLY	REP	ROL
ROR	RTI	RTL	RTS	SBC	SEC	SED	SEI	SEP	STA
STP	STX	STY	STZ	TAX	TAY	TCD	TCS	TDC	TRB
TSB	TSC	TSX	TXA	TXS	TXY	TYA	TYX	WAI	WDM
XBA	XCE

Instructions By Category

Category	Instructions
Arithmetic	ADC , SBC
Boolean	AND , EOR , ORA
Shift	ASL , LSR , ROL , ROR
Branch	BCC , BCS , BEQ , BMI , BNE , BPL , BRA , BRK , BRL , BVC , BVS
Test	BIT , TRB , TSB
Flags	CLC , CLD , CLI , CLV , REP , SEC , SED , SEI , SEP
Compare	CMP , CPX , CPY
Interrupt	COP , WAI
Inc/Dec	DEC , DEX , DEY , INC , INX , INY
Flow	JMP , JML , JSL , JSR , NOP , RTI , RTL , RTS , WDM
Load	LDA , LDX , LDY
Block Move	MVN , MVP
Stack	PEA , PEI , PER , PHA , PHB , PHD , PHK , PHP , PHX , PHY , PLA , PLB , PLD , PLP , PLX , PLY
Store	STA , STP , STX , STY , STZ
Register Swap	TAX , TAY , TCD , TCS , TDC , TSC , TSX , TXA , TXS , TXY , TYA , TYX , XBA , XCE

ADC

Add with Carry

SYNTAX           MODE       HEX LEN CYCLES      FLAGS   
ADC #$20/#$1234  imm        69  3-m 3-m         nv....zc .
ADC $20          dir        65  2   4-m+w       nv....zc .
ADC $20,X        dir,X      75  2   5-m+w       nv....zc .
ADC $20,S        stk,S      63  2   5-m         nv....zc .
ADC $1234        abs        6D  3   5-m         nv....zc .
ADC $1234,X      abs,X      7D  3   6-m-x+x*p   nv....zc .
ADC $1234,Y      abs,Y      79  3   6-m-x+x*p   nv....zc .
ADC $FEDBCA      long       6F  4   6-m         nv....zc .
ADC $FEDCBA,X    long,X     7F  4   6-m         nv....zc .
ADC ($20)        (dir)      72  2   6-m+w       nv....zc .
ADC ($20),Y      (dir),Y    71  2   7-m+w-x+x*p nv....zc .
ADC ($20,X)      (dir,X)    61  2   7-m+w       nv....zc .
ADC ($20,S),Y    (stk,S),Y  73  2   8-m         nv....zc .
ADC [$20]        [dir]      67  2   7-m+w       nv....zc .
ADC [$20],Y      [dir],Y    77  2   7-m+w       nv....zc .

ADC adds the accumulator (.A), the supplied operand, and the Carry bit (0 or 1). The result is stored in .A.

Since Carry is always added in, you should always remember to use CLC (Clear Carry) before performing an addition operation. When adding larger numbers (16, 24, 32, or more bits), you can use the Carry flag to chain additions.

Here is an example of a 16-bit add, when in 8 bit mode:

CLC
LDA Addend1
ADC Addend2
STA Result1
LDA Addend1+1  ; Reads the high byte of the addend
ADC Addend2+1  ; (the +1 refers to the *address* of Addend, not the value)
STA Result1+1  ;
done:
; the final result is at Result1

Flags:

n is set when the high bit of .A is set. This indicates a negative number when using Two’s Complement signed values.
v (overflow) is set when the sum exceeds the maximum signed value for .A. (More on that below). * n is set when the high bit is 1.
z is set when the result is zero. This is useful for loop counters and can be tested with BEQ and BNE. (BEQ and BNE test the Zero bit, which is also the “equal” bit when performing subtraction or Compare operations.)
c is set when the unsigned result exceeds the register’s capacity (255 or 65535).

Overflow vs Carry

The CPU detects addition that goes past the 7 or 15 bit boundary of a signed number, as well as the 8 bit boundary of an unsigned number.

In 8-bit mode, when you add two positive numbers that result in a sum higher than 127 or add two negative numbers that result in a sum below -128, you will get a signed overflow, and the v flag will be set.

When the sum of the two numbers exceeeds 255 or 65535, then the Carry flag will be set. This bit can be added to the next higher byte with ADC #0.

CLC
LDA #$7F
ADC #$10
BRK

	x0	x1	x2	x3	x4	x5	x6	x7	x8	x9	xA	xB	xC	xD	xE	xF
0x	BRK	ORA	COP	ORA	TSB	ORA	ASL	ORA	PHP	ORA	ASL	PHD	TSB	ORA	ASL	ORA
1x	BPL	ORA	ORA	ORA	TRB	ORA	ASL	ORA	CLC	ORA	INC	TCS	TRB	ORA	ASL	ORA
2x	JSR	AND	JSL	AND	BIT	AND	ROL	AND	PLP	AND	ROL	PLD	BIT	AND	ROL	AND
3x	BMI	AND	AND	AND	BIT	AND	ROL	AND	SEC	AND	DEC	TSC	BIT	AND	ROL	AND
4x	RTI	EOR	WDM	EOR	MVP	EOR	LSR	EOR	PHA	EOR	LSR	PHK	JMP	EOR	LSR	EOR
5x	BVC	EOR	EOR	EOR	MVN	EOR	LSR	EOR	CLI	EOR	PHY	TCD	JML	EOR	LSR	EOR
6x	RTS	ADC	PER	ADC	STZ	ADC	ROR	ADC	PLA	ADC	ROR	RTL	JMP	ADC	ROR	ADC
7x	BVS	ADC	ADC	ADC	STZ	ADC	ROR	ADC	SEI	ADC	PLY	TDC	JMP	ADC	ROR	ADC
8x	BRA	STA	BRL	STA	STY	STA	STX	STA	DEY	BIT	TXA	PHB	STY	STA	STX	STA
9x	BCC	STA	STA	STA	STY	STA	STX	STA	TYA	STA	TXS	TXY	STZ	STA	STZ	STA
Ax	LDY	LDA	LDX	LDA	LDY	LDA	LDX	LDA	TAY	LDA	TAX	PLB	LDY	LDA	LDX	LDA
Bx	BCS	LDA	LDA	LDA	LDY	LDA	LDX	LDA	CLV	LDA	TSX	TYX	LDY	LDA	LDX	LDA
Cx	CPY	CMP	REP	CMP	CPY	CMP	DEC	CMP	INY	CMP	DEX	WAI	CPY	CMP	DEC	CMP
Dx	BNE	CMP	CMP	CMP	PEI	CMP	DEC	CMP	CLD	CMP	PHX	STP	JML	CMP	DEC	CMP
Ex	CPX	SBC	SEP	SBC	CPX	SBC	INC	SBC	INX	SBC	NOP	XBA	CPX	SBC	INC	SBC
Fx	BEQ	SBC	SBC	SBC	PEA	SBC	INC	SBC	SED	SBC	PLX	XCE	JSR	SBC	INC	SBC


ADC	AND	ASL	BCC	BCS	BEQ	BIT	BMI	BNE	BPL
BRA	BRK	BRL	BVC	BVS	CLC	CLD	CLI	CLV	CMP
COP	CPX	CPY	DEC	DEX	DEY	EOR	INC	INX	INY
JMP	JML	JSL	JSR	LDA	LDX	LDY	LSR	MVN	MVP
NOP	ORA	PEA	PEI	PER	PHA	PHB	PHD	PHK	PHP
PHX	PHY	PLA	PLB	PLD	PLP	PLX	PLY	REP	ROL
ROR	RTI	RTL	RTS	SBC	SEC	SED	SEI	SEP	STA
STP	STX	STY	STZ	TAX	TAY	TCD	TCS	TDC	TRB
TSB	TSC	TSX	TXA	TXS	TXY	TYA	TYX	WAI	WDM
XBA	XCE

	x0	x1	x2	x3	x4	x5	x6	x7	x8	x9	xA	xB	xC	xD	xE	xF
0x	BRK	ORA	COP	ORA	TSB	ORA	ASL	ORA	PHP	ORA	ASL	PHD	TSB	ORA	ASL	ORA
1x	BPL	ORA	ORA	ORA	TRB	ORA	ASL	ORA	CLC	ORA	INC	TCS	TRB	ORA	ASL	ORA
2x	JSR	AND	JSL	AND	BIT	AND	ROL	AND	PLP	AND	ROL	PLD	BIT	AND	ROL	AND
3x	BMI	AND	AND	AND	BIT	AND	ROL	AND	SEC	AND	DEC	TSC	BIT	AND	ROL	AND
4x	RTI	EOR	WDM	EOR	MVP	EOR	LSR	EOR	PHA	EOR	LSR	PHK	JMP	EOR	LSR	EOR
5x	BVC	EOR	EOR	EOR	MVN	EOR	LSR	EOR	CLI	EOR	PHY	TCD	JML	EOR	LSR	EOR
6x	RTS	ADC	PER	ADC	STZ	ADC	ROR	ADC	PLA	ADC	ROR	RTL	JMP	ADC	ROR	ADC
7x	BVS	ADC	ADC	ADC	STZ	ADC	ROR	ADC	SEI	ADC	PLY	TDC	JMP	ADC	ROR	ADC
8x	BRA	STA	BRL	STA	STY	STA	STX	STA	DEY	BIT	TXA	PHB	STY	STA	STX	STA
9x	BCC	STA	STA	STA	STY	STA	STX	STA	TYA	STA	TXS	TXY	STZ	STA	STZ	STA
Ax	LDY	LDA	LDX	LDA	LDY	LDA	LDX	LDA	TAY	LDA	TAX	PLB	LDY	LDA	LDX	LDA
Bx	BCS	LDA	LDA	LDA	LDY	LDA	LDX	LDA	CLV	LDA	TSX	TYX	LDY	LDA	LDX	LDA
Cx	CPY	CMP	REP	CMP	CPY	CMP	DEC	CMP	INY	CMP	DEX	WAI	CPY	CMP	DEC	CMP
Dx	BNE	CMP	CMP	CMP	PEI	CMP	DEC	CMP	CLD	CMP	PHX	STP	JML	CMP	DEC	CMP
Ex	CPX	SBC	SEP	SBC	CPX	SBC	INC	SBC	INX	SBC	NOP	XBA	CPX	SBC	INC	SBC
Fx	BEQ	SBC	SBC	SBC	PEA	SBC	INC	SBC	SED	SBC	PLX	XCE	JSR	SBC	INC	SBC


ADC	AND	ASL	BCC	BCS	BEQ	BIT	BMI	BNE	BPL
BRA	BRK	BRL	BVC	BVS	CLC	CLD	CLI	CLV	CMP
COP	CPX	CPY	DEC	DEX	DEY	EOR	INC	INX	INY
JMP	JML	JSL	JSR	LDA	LDX	LDY	LSR	MVN	MVP
NOP	ORA	PEA	PEI	PER	PHA	PHB	PHD	PHK	PHP
PHX	PHY	PLA	PLB	PLD	PLP	PLX	PLY	REP	ROL
ROR	RTI	RTL	RTS	SBC	SEC	SED	SEI	SEP	STA
STP	STX	STY	STZ	TAX	TAY	TCD	TCS	TDC	TRB
TSB	TSC	TSX	TXA	TXS	TXY	TYA	TYX	WAI	WDM
XBA	XCE